Transforming established SoC design paradigms into system-level fabrics capable of supporting next-generation AI, HPC, and data center workloads.

Build configurable PCIe subsystems spanning local expansion, shared resource domains, and longer-reach topologies.

One toolchain means one team. The DSP specialists, the ML engineers, and the firmware developers work in the same environment ...

Synopsys’ 3D PCIe 6.0 test-chip demonstration shows that 64.0 GT/s PCIe connectivity, with up to 128.0 GB/s delivered through an 8-lane configuration using PAM4 signaling, can be implemented and ...

Even though the benefits are accepted, a combined hardware/software development flow is hampered by a lot of challenges.

Data centers are notorious energy consumers. On the one hand, ongoing efforts attempt to reduce electronics power to keep overall power from growing. On the other hand, data centers are provided with ...

Rising power density and chiplet complexity drive thermal considerations earlier in the design process. Thermal is becoming an architectural constraint, requiring trade-offs in power, performance, ...

Advanced packaging enables semiconductor companies to integrate more dies and increasingly heterogeneous components using ...

Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, ...

Researchers at National Yang Ming Chiao Tung University and TSMC published a technical paper titled “High contrast EUV ...

Cost per token is causing EDA design budgets to balloon; what comes next isn’t entirely clear yet. Discussions have shifted ...

Semiconductors are no longer viewed as purely commercial products. They are now deeply connected to AI, economic ...