EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
EDN

Building an FPGA FIFO without using logic resources

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
Semiconductor Engineering

Simulating HW with C Speed and RTL Accuracy for HLS Designs (Georgia Tech)

A new technical paper titled “OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs” was published by researchers at Georgia Institute of Technology. “High-Level ...
Electronic Design

Functional Analyzer Scopes Out SoC Defects In RTL

Expanding predictive analysis technology into the functional space, the Periscope functional analysis tool helps engineers quickly determine whether their RTL design descriptions are functionally ...
Semiconductor Engineering

Micro-Architectural Exploration For Low Power Design

The adoption of finFET technology has created a tectonic shift in the chip design landscape. In addition to better performance (within the same power envelope) and higher reliability, finFETs have ...